University of Portland Senior Design Demonstration - 4 digit counter implemented on two Xilinx CPLDs. All CPLD code has been autogenerated by our B Squared Logic to ABEL converter.
Channel: Howto & Style Uploaded: November 30, 1999 at 12:00 am Author: jsquintz
wouldn't fit with 7 segment decoders on chip. could be possible but this was a simple proof of concept the ABEL code autogeneration software we wrote. The counter wasn't designed for size, but rather because the design files were already handy.
